The EP103 LVDS transmitter supports transmission between the host and the flat panel display up to SXGA+ resolutions. The transmitter converts 3×10 bits of Low Voltage TTL data and 3 control bits into 4 LVDS (Low Voltage Differential Signal) data streams. At a maximum input clock rate of 135MHz, each LVDS differential data pair speed is 945Mbps, providing a total throughput of 3.78Gbps. The transmitter can be configured to input clock rising edge or falling edge strobe through an external pin. Support 10MHz to 135MHz clock rates for HVGA to SXGA+ resolution Up to 3.78Gbps bandwidth PLL requires no external components Cycletocycle jitter rejection 3.3V to 1.8V Low Voltage TTL tolerant Input Programmable data and control strobe select Power down mode supported LQFP64 package
Chine
Super mini porte-clés avec câble USB et connexion 4 en 1. Avec fonction de charge et de transfert de données
Demander un devisCréez une seule demande et obtenez plusieurs devis de fournisseurs vérifiés.